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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2000 mos integrated circuit mc-45d32cd641 document no. m14899ej1v0ds00 (1st edition) date published june 2000 ns cp(k) printed in japan preliminary data sheet 32 m-word by 64-bit ddr synchronous dynamic ram module unbuffered type description the mc-45d32cd641 is a 33,554,432 words by 64 bits ddr synchronous dynamic ram module on which 16 pieces of 128m ddr sdram: m pd45d128842 are assembled. these modules provide high density and large quantities of memory in a small space without utilizing the surface- mounting technology on the printed circuit board. decoupling capacitors are mounted on power supply line for noise reduction. features 33,554,432 words by 64 bits organization clock frequency part number /cas latency clock frequency module type (max.) mc-45d32cd641kfa-c75 cl = 2.5 133 mhz ddr sdram cl = 2 100 mhz unbuffered dimm mc-45d32cd641kfa-c80 cl = 2.5 125 mhz design specification cl = 2 100 mhz rev.0.9 compliant fully synchronous dynamic ram with all signals except dm, dqs and dq referenced to a positive clock edge double data rate interface differential clk (/clk) input data inputs and dm are synchronized with both edges of dqs data outputs and dqs are synchronized with a cross point of clk and /clk quad internal banks operation possible to assert random column address in every clock cycle programmable mode register set /cas latency (2, 2.5) burst length (2, 4, 8) wrap sequence (sequential / interleave) automatic precharge and controlled precharge cbr (auto) refresh and self refresh 2.5 v 0.2 v power supply for v dd 2.5 v 0.2 v power supply for v dd q sstl_2 compatible with all signals 4,096 refresh cycles / 64 ms burst termination by precharge command and burst stop command 184-pin dual in-line memory module (pin pitch = 1.27 mm) unbuffered type serial pd
preliminary data sheet m14899ej1v0ds00 2 mc-45d32cd641 ordering information part number clock frequency (max.) package mounted devices mc-45d32cd641kfa-c75 133 mhz 184-pin dual in-line memory module 16 pieces of m pd45d128842g5 (rev. k) (socket type) (10.16 mm (400) tsop (ii)) mc-45d32cd641kfa-c80 125 mhz edge connector: gold plated 31.75 mm height
preliminary data sheet m14899ej1v0ds00 3 mc-45d32cd641 pin configuration 184-pin dual in-line memory module socket type (edge connector: gold plated) 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 v ss dq36 dq37 v dd dm4/dqs13 dq38 dq39 v ss dq44 /ras dq45 v dd q /s0 /s1 dm5/dqs14 v ss dq46 dq47 nc v dd q dq52 dq53 nc v dd dm6/dqs15 dq54 dq55 v dd q nc dq60 dq61 v ss dm7/dqs16 dq62 dq63 v dd q sa0 sa1 sa2 v dd spd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 dq32 v dd q dq33 dqs4 dq34 v ss ba0 dq35 dq40 v dd q /we dq41 /cas v ss dqs5 dq42 dq43 v dd nc dq48 dq49 v ss ck2 /ck2 v dd q dqs6 dq50 dq51 v ss v dd id dq56 dq57 v dd dqs7 dq58 dq59 v ss nc sda scl v ref dq0 v ss dq1 dqs0 dq2 v dd dq3 nc /reset v ss dq8 dq9 dqs1 v dd q ck1 /ck1 v ss dq10 dq11 cke0 v dd q dq16 dq17 dqs2 v ss a9 dq18 a7 v dd q dq19 a5 dq24 v ss dq25 dqs3 a4 v dd dq26 dq27 a2 v ss a1 nc nc v dd nc a0 nc v ss nc ba1 v ss dq4 dq5 v dd q dm0/dqs9 dq6 dq7 v ss nc nc nc v dd q dq12 dq13 dm1/dqs10 v dd dq14 dq15 nc v dd q nc dq20 nc v ss dq21 a11 dm2/dqs11 v dd dq22 a8 dq23 v ss a6 dq28 dq29 v dd q dm3/dqs12 a3 dq30 v ss dq31 nc nc v dd q ck0 /ck0 v ss nc a10 nc v dd q nc a0 - a11 : address inputs [row: a0 - a11, column: a0 - a9] ba0, ba1 : sdram bank select dq0 - dq63 : data inputs/outputs ck0 - ck2 : clock input (positive line of differential pair) /ck0 - /ck2 : clock input (negative line of differential pair) cke0 : clock enable input /s0, /s1 : chip select input /ras : row address strobe /cas : column address strobe /we : write enable dqs0 - dqs7 : low data strobe dm(0 - 7) / dqs(9 - 16) : low data masks / high data strobe sa0 - sa2 : address input for eeprom sda : serial data i/o for pd scl : clock input for pd v dd : power supply v ss : ground v dd id : v dd identification flag v dd q : power supply for dq and dqs v ref : input reference v dd spd : power supply for eeprom nc : no connection /reset : reset input /xxx indicates active low si gnal.
preliminary data sheet m14899ej1v0ds00 4 mc-45d32cd641 block diagram dm0/dqs9 dm /s dq 0 dq 1 dq 2 dq 3 dq 7 dq 6 dq 1 dq 0 v dd d0 - d15 d0 - d15 d0 ba0, ba1 ba0, ba1 : sdrams d0 - d15 serial pd sda a0 a1 a2 sa0 sa1 sa2 scl a0 - a11 a0 - a11 : sdrams d0 - d15 /ras /ras : sdrams d0 - d15 /cas /cas : sdrams d0 - d15 cke0 cke0 : sdrams d0 - d15 /we /we : sdrams d0 - d15 ck0, /ck0 ck, /ck : sdrams d3, d4, d11, d12 ck1, /ck1 ck, /ck : sdrams d0, d1, d2, d8, d9, d10 ck2, /ck2 ck, /ck : sdrams d5, d6, d7, d13, d14, d15 v ss /s0 /s1 dq 4 dq 5 dq 6 dq 7 dq 5 dq 4 dq 3 dq 2 dqs dqs0 dm1/dqs10 dm /s dq 8 dq 9 dq 10 dq 11 d1 dq 12 dq 13 dq 14 dq 15 dqs dqs1 dm2/dqs11 dm /s dq 16 dq 17 dq 18 dq 19 d2 dq 20 dq 21 dq 22 dq 23 dqs dqs2 dm3/dqs12 dm /s dq 24 dq 25 dq 26 dq 27 d3 dq 28 dq 29 dq 30 dq 31 dqs dqs3 dm4/dqs13 dm /s dq 32 dq 33 dq 34 dq 35 dq 7 dq 6 dq 1 dq 0 d4 dq 36 dq 37 dq 38 dq 39 dq 5 dq 4 dq 3 dq 2 dqs dqs4 dm5/dqs14 dm /s dq 40 dq 41 dq 42 dq 43 d5 dq 44 dq 45 dq 46 dq 47 dqs dqs5 dm6/dqs15 dm /s dq 48 dq 49 dq 50 dq 51 d6 dq 52 dq 53 dq 54 dq 55 dqs dqs6 dm7/dqs16 dm /s dq 56 dq 57 dq 58 dq 59 d7 dq 60 dq 61 dq 62 dq 63 dqs dm /s dq 0 dq 1 dq 6 dq 7 d8 dq 2 dq 3 dq 4 dq 5 dqs dm /s d9 dqs dm /s d10 dqs dm /s d11 dqs dm /s dq 0 dq 1 dq 6 dq 7 d12 dq 2 dq 3 dq 4 dq 5 dqs dm /s d13 dqs dm /s d14 dqs dm /s d15 dqs dqs7 v dd q d0 - d15 v ref d0 - d15 v dd id dq 7 dq 6 dq 1 dq 0 dq 5 dq 4 dq 3 dq 2 dq 7 dq 6 dq 1 dq 0 dq 5 dq 4 dq 3 dq 2 dq 7 dq 6 dq 1 dq 0 dq 5 dq 4 dq 3 dq 2 dq 0 dq 1 dq 6 dq 7 dq 2 dq 3 dq 4 dq 5 dq 0 dq 1 dq 6 dq 7 dq 2 dq 3 dq 4 dq 5 dq 0 dq 1 dq 6 dq 7 dq 2 dq 3 dq 4 dq 5 dq 7 dq 6 dq 1 dq 0 dq 5 dq 4 dq 3 dq 2 dq 7 dq 6 dq 1 dq 0 dq 5 dq 4 dq 3 dq 2 dq 7 dq 6 dq 1 dq 0 dq 5 dq 4 dq 3 dq 2 dq 0 dq 1 dq 6 dq 7 dq 2 dq 3 dq 4 dq 5 dq 0 dq 1 dq 6 dq 7 dq 2 dq 3 dq 4 dq 5 dq 0 dq 1 dq 6 dq 7 dq 2 dq 3 dq 4 dq 5 remarks 1. the value of all resistors of dqs, dqss, dm/dqss is 22 w . 2. d0 C d15: m pd45d128842 (4m words 8 bits 4 banks)
preliminary data sheet m14899ej1v0ds00 5 mc-45d32cd641 electrical specifications all voltages are referenced to v ss (gnd). after power up, wait more than 1 ms and then, execute power on sequence and cbr (auto) refresh before proper device operation is achieved. absolute maximum ratings parameter symbol condition rating unit voltage on power supply pin relative to v ss v dd , v dd q C0.5 to +3.6 v voltage on input pin relative to v ss v t C0.5 to +3.6 v short circuit output current i o 50 ma power dissipation p d 12 w storage temperature t stg C55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v dd 2.3 2.5 2.7 v supply voltage for dq, dqs v dd q 2.3 2.5 2.7 v input reference voltage v ref 0.49 v dd q 0.51 v dd qv termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v high level dc input voltage v ih (dc) v ref + 0.15 v dd + 0.3 v low level dc input voltage v il (dc) - 0.3 v ref - 0.15 v input differential voltage (clk and /clk) v id (dc) 0.36 v dd q + 0.6 v input crossing point voltage (clk and /clk) v ix 0.5 v dd qC0.2 0.5 v dd q+0.2 v operating ambient temperature t a 070 c capacitance (t a = 25 c, f = 100 mhz) parameter symbol test condition min. typ. max. unit input capacitance c i1 a0 - a11, ba0, ba1, /ras, /cas, /we tbd tbd pf c i2 ck0 - ck2, /ck0 - /ck2 tbd tbd c i3 cke0 tbd tbd c i4 /s0, /s1 tbd tbd data input/output capacitance c i/o1 dm(0-7)/dqs(9-16), dqs0 - dqs7 tbd tbd pf c i/o2 dq0 - dq63 tbd tbd
preliminary data sheet m14899ej1v0ds00 6 mc-45d32cd641 dc characteristics 1 (recommended operating conditions unless otherwise noted) parameter symbol test condition /cas latency grade min. max. unit notes -c75 tbd ma operating current (act-pre) i dd0 t rc = t rc(min.) , t ck = t ck (min.) , one bank, active-precharge, dq, dm and dqs inputs changing twice per clock cycle, address and control inputs changing once per clock cycle -c80 tbd cl = 2 -c75 tbd ma 1 -c80 tbd cl = 2.5 -c75 tbd operating current (act-read-pre) i dd1 t rc = t rc(min.) , t ck = t ck (min.) , one bank, active-read-precharge, i o = 0 ma, burst length = 2, address and control inputs changing once per clock cycle -c80 tbd precharge power down standby current i dd2p cke v il(max.) , t ck = t ck(min.) , all banks idle, power down mode tbd ma idle standby current i dd2n cke 3 v ih(min.) , t ck = t ck(min.) , /cs 3 v ih(min.) , all banks idle, address and other control inputs changing once per clock cycle tbd ma active power down standby current i dd3p cke v il(max.) , t ck = t ck(min.) , one bank active, power down mode tbd ma active standby current i dd3n /cs 3 v ih(min.) , cke 3 v ih(min.) , t ck = t ck(min.) , t rc = t ras(max.) , one bank, active-precharge, dq, dm and dqs inputs changing twice per clock cycle, address and other control inputs changing once per clock cycle tbd ma cl = 2 -c75 tbd ma 2 -c80 tbd cl = 2.5 -c75 tbd operating current (burst read) i dd4r t ck = t ck(min.) , continuous burst read, burst length = 2, i o = 0ma, one bank active, address and control inputs changing once per clock cycle -c80 tbd cl = 2 -c75 tbd ma 2 -c80 tbd cl = 2.5 -c75 tbd operating current (burst write) i dd4w t ck = t ck(min.) , continuous burst write, burst length = 2, one bank active, address and control inputs changing once per clock cycle -c80 tbd cbr (auto) refresh current i dd5 t rfc = t rfc(min.) -c75 tbd ma -c80 tbd self refresh current i dd6 cke 0.2 v tbd ma notes 1. i dd1 depends on output loading and cycle rates. specified values are obtained with the output open. 2. i dd4r and i dd4w depend on output loading and cycle rates. specified values are obtained with the output open. dc characteristics 2 (recommended operating conditions unless otherwise noted) parameter symbol test condition min. max. unit notes input leakage current i i(l) v i = 0 to 3.6 v, all other pins not under test = 0 v tbd tbd m a output leakage current i o(l) d out is disabled, v o = 0 to v dd q + 0.3 v tbd tbd m a output high current i oh v out = v dd q - 0.43 v tbd ma output low current i ol v out = 0.35 v tbd ma
preliminary data sheet m14899ej1v0ds00 7 mc-45d32cd641 ac characteristics (recommended operating conditions unless otherwise noted) test conditions parameter symbol value unit notes input reference voltage (input timing measurement reference level) v ref v dd q x 0.5 v termination voltage (output timing measurement reference level) v tt v ref v1 high level ac input voltage v ih (ac) v ref + 0.31 v low level ac input voltage v il (ac) v ref - 0.31 v input differential voltage (ck0 - ck2 and /ck0 - /ck2) v id (ac) 0.7 v input signal slew rate slew 1 v/ns 2 notes 1. output waveform timing is measured where the output signal crosses through the v tt level. 2. slew rate is to be maintained in the v il (ac) to v ih (ac) range of the input signal swing. slew = (v ih (ac)- v il (ac))/ d t output r t = 50 w c load = 30 pf v tt
preliminary data sheet m14899ej1v0ds00 8 mc-45d32cd641 synchronous characteristics parameter symbol -c75 (pc266b) -c80 (pc200) unit note min. max. min. max. clock cycle time cl = 2.5 t ck 7.515815ns cl = 2 10151015 clk high-level width t ch 0.45 0.55 0.45 0.55 t ck clk low-level width t cl 0.45 0.55 0.45 0.55 t ck dq output access time from clk, /clk t ac C0.75 0.75 C0.8 0.8 ns dqs output access time from clk, /clk t dqsck C0.75 0.75 C0.8 0.8 ns dqs-dq skew (for dqs and associated dq signals) t dqsq C0.5 0.5 C0.6 0.6 ns dqs-dq skew (for dqs and all dq signals) t dqsqa C0.5 0.5 C0.6 0.6 ns data out low-impedance time from clk, /clk t lz C0.75 0.75 C0.8 0.8 ns data out high-impedance time from clk, /clk t hz C0.75 0.75 C0.8 0.8 ns half clock period t hp t ch , t cl t ch , t cl ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp C 0.75 t hp C 1 ns dq and dm input setup time t ds 0.5 0.6 ns dq and dm input hold time t dh 0.5 0.6 ns dq and dm input pulse width (for each input) t dipw 1.75 2 ns dqs write preamble setup time t wpres 00ns dqs write preamble t wpre 0.25 0.25 t ck write postamble t wpst 0.4 0.6 0.4 0.6 t ck write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs falling edge to clk setup time t dss 0.2 0.2 t ck dqs falling edge hold time from clk t dsh 0.2 0.2 t ck address and control input setup time t is 0.9 1.1 ns address and control input hold time t ih 0.9 1.1 ns address and control input pulse width t ipw 2.2 2.5 ns internal write to read command delay t wtr 11t ck remark these specifications are applied to the monolithic device.
preliminary data sheet m14899ej1v0ds00 9 mc-45d32cd641 asynchronous characteristics parameter symbol -c75(pc266b) -c80(pc200) unit min. max. min. max. act to ref/act command period (operation) t rc 65 70 ns ref to ref/act command period (refresh) t rfc 75 80 ns act to pre command period t ras 45 120,000 50 120,000 ns pre to act command period t rp 20 20 ns act to read/write delay t rcd 20 20 ns act(one) to act(another) command period t rrd 15 15 ns write recovery time t wr 15 15 ns auto precharge write recovery time + precharge time t dal 35 35 ns mode register set command cycle time t mrd 15 15 ns exit self refresh to command t xsnr 75 80 ns refresh time (4,096 refresh cycles) t ref 64 64 ms
preliminary data sheet m14899ej1v0ds00 10 mc-45d32cd641 serial pd (1/2) byte no. function described hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes 0 defines the number of bytes written into serial pd memory 80h 1 0 0 0 0 0 0 0 128 bytes 1 total number of bytes of serial pd memory 08h 0 0 0 0 1 0 0 0 256 bytes 2 fundamental memory type 07h 0 0 0 0 0 1 1 1 ddr sdram 3 number of rows 0ch 0 0 0 0 1 1 0 0 12 rows 4 number of columns 0ah 0 0 0 0 1 0 1 0 10 columns 5 number of banks 02h 0 0 0 0 0 0 1 0 2 banks 6 data width 40h 0 1 0 0 0 0 0 0 64 bits 7 data width (continued) 00h 0 0 0 0 0 0 0 0 0 8 voltage interface 04h 0 0 0 0 0 1 0 0 sstl2 9 cl = 2.5 cycle time -c75 75h 0 1 1 1 0 1 0 1 7.5 ns -c80 80h 1 0 0 0 0 0 0 0 8 ns 10 cl = 2.5 access time -c75 75h 0 1 1 1 0 1 0 1 0.75 ns -c80 80h 1 0 0 0 0 0 0 0 0.8 ns 11 dimm configuration type 00h 0 0 0 0 0 0 0 0 none 12 refresh rate/type 80h 1 0 0 0 0 0 0 0 normal 13sdram width 08h00001000x8 14 error checking sdram width 00h 0 0 0 0 0 0 0 0 none 15 minimum clock delay 01h 0 0 0 0 0 0 0 1 1 clock 16 burst length supported 0eh 0 0 0 0 1 1 1 0 2, 4, 8 17 number of banks on each sdram 04h 0 0 0 0 0 1 0 0 4 banks 18 /cas latency supported 0ch 0 0 0 0 1 1 0 0 2, 2.5 19 /cs latency supported 01h 0 0 0 0 0 0 0 1 0 20 /we latency supported 02h 0 0 0 0 0 0 1 0 1 21 sdram module attributes 20h 0 0 1 0 0 0 0 0 differential clock 22 sdram device attributes : general 00h 0 0 0 0 0 0 0 0 v dd 0.2 v 23 cl = 2 cycle time -c75 a0h 1 0 1 0 0 0 0 0 10 ns -c80 a0h 1 0 1 0 0 0 0 0 10 ns 24 cl = 2 access time -c75 75h 0 1 1 1 0 1 0 1 0.75 ns -c80 80h 1 0 0 0 0 0 0 0 0.8 ns 25-26 27 t rp(min.) -c75 50h 0 1 0 1 0 0 0 0 20 ns -c80 50h 0 1 0 1 0 0 0 0 20 ns 28 t rrd(min.) -c75 3ch 0 0 1 1 1 1 0 0 15 ns -c80 3ch 0 0 1 1 1 1 0 0 15 ns 29 t rcd(min.) -c75 50h 0 1 0 1 0 0 0 0 20 ns -c80 50h 0 1 0 1 0 0 0 0 20 ns 30 t ras(min.) -c75 2dh 0 0 1 0 1 1 0 1 45 ns -c80 32h 0 0 1 1 0 0 1 0 50 ns 31 module bank density 20h 0 0 1 0 0 0 0 0 128m bytes
preliminary data sheet m14899ej1v0ds00 11 mc-45d32cd641 (2/2) byte no. function described hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes 32 command and address signal input setup time c0h110000001.2 ns 33 command and address signal input hold time c0h110000001.2 ns 34 data signal input setup time 60h 0 1 1 0 0 0 0 0 0.6 ns 35 data signal input hold time 60h 0 1 1 0 0 0 0 0 0.6 ns 36-61 62spd revision 00h00000000 63 checksum for bytes 0 - 62 -c75 1dh 0 0 0 1 1 1 0 1 -c8043h01000011 64-71 manufactures jedec id code 72 manufacturing location 73-90 manufactures p/n 91 revision code 93-94 manufacturing date 95-99 assembly serial number 100-127 mfg specific 00h 0 0 0 0 0 0 0 0 timing chart refer to the m pd45d128442, 45d128842, 45d128164 data sheet (m13852e).
preliminary data sheet m14899ej1v0ds00 12 mc-45d32cd641 package drawing 184-pin dual in-line module (socket type) item millimeters a a1 b c1 c2 d e g h 133.35 64.77 1.80 3.80 49.53 133.35 0.13 1.27 (t.p.) j 6.35 j1 c i 6.35 10.00 j2 k m n p q r s 31.75 0.13 4.0 max. 17.80 4.0 min. 2.50 4.0 u 19.80 23.38 t 1.27 0.1 0.2 0.15 1.0 0.05 2.50 0.15 3.0 min. f j1 (area b) u m j2 (area a) e c p q detail of a part c2 c1 t r a (optional holes) n k a (area b) a1 (area a) j i b g d s h m
preliminary data sheet m14899ej1v0ds00 13 mc-45d32cd641 [memo]
preliminary data sheet m14899ej1v0ds00 14 mc-45d32cd641 [memo]
preliminary data sheet m14899ej1v0ds00 15 mc-45d32cd641 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
mc-45d32cd641 caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ic, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. m8e 00. 4 the information in this document is current as of june, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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